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KEY TAKEAWAYS

•   The growing demand for artificial intelligence (AI) and machine learning is driving innovations in chip fabrication and advances in memory technologies and highbandwidth interconnects such as photonic links, all of which are essential for enhancing computational power, managing energy efficiency, and meeting the increasing data needs of modern applications.

•   Semiconductor manufacturing is the most precise manufacturing process that exists. It is used to advance work in energy and biotechnology in addition to information technology and AI.

•   Strategic technology containment efforts directed against China help constrain Chinese capabilities in the short term. However, they are likely to drive China into a technology posture that is considerably more decoupled from the West and hence less vulnerable to Western pressure in the future.

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Overview

Semiconductors, often in the form of microchips, are crucial components in everything from smartphones and cars to advanced weapons and navigation systems used by the military. Chips must be designed and then subsequently manufactured in facilities known as “fabs,” which can cost billions of dollars and take several years to build. Only a few companies both design and make chips; most specialize in either design or manufacturing. In 2024, Taiwan Semiconductor Manufacturing Company controlled over 60 percent of the world’s contract manufacturing and 90 percent of the manufacturing of advanced chips. With a large percentage of the world’s chip factories located in Taiwan, the global supply chain for chips remains fragile.

 

KEY DEVELOPMENTS

Moore’s Law, Past and Future For over half a century, a phenomenon known as Moore’s law has governed developments in the semiconductor industry. This refers to a trend in which the number of transistors on a chip of the same size and cost has doubled roughly every couple of years, effectively doubling the chip’s processing power. Moore’s law is not a law of physics but an observed trend driven by improvements in manufacturing tools and other factors that have been so consistent that everyone expects the cost of computing to keep decreasing with time. However, there are indications that Moore’s law has slowed down and that its end may be in sight.

This is happening just as artificial intelligence (AI) and machine learning (ML) are driving a surge in demand for computing resources—especially for specialized hardware such as advanced graphical processing units (GPUs), which power the development and training of many AI and ML models.

Of note: For at least a decade, the name of a chip technology, such as “sevennanometer chip,” has not been an indicator of the size of the chip’s smallest feature. Rather it has been a generational label referring to improved circuit density as the result of extending designs vertically and adopting new materials.

Chiplets and 2.5-D Integration As Moore’s law slows, novel computing advancements are needed. Chiplets are small, modular chips that specialize in specific functions and can be combined in ways that deliver more energyefficient processing power than large, monolithic chips. In 2.5-D integration, an interposer—a specialized substrate—is used to connect chiplets, facilitating faster, more energy-efficient communication. This approach allows high-density memory, high-performance compute units, and communication chips to reside side by side, boosting bandwidth, performance, and power efficiency while reducing the need for full integration on a single chip.

High-Power Density To further improve system performance, compute and memory elements can be moved closer to each other, reducing time delays in sending signals between components. However, closer packing of these elements increases the heat generated per square centimeter. Modern systems generate large amounts of heat: A single GPU generates about a kilowatt of heat and an advanced cluster of them about a megawatt. Traditional air cooling is inadequate, so liquid-based systems are essential.

Memory Technology Developments Innovations like stacking and new materials are advancing memory technology, enabling higher density and performance vital for AI and big data. DRAM and flash have evolved with 3-D structures and complex packaging to support high-bandwidth memory. Magnetoresistive and phase-change memories offer speed and energy benefits.

 

Over the Horizon

3-D Heterogenous Integration In 3-D heterogeneous integration, different semiconductor components, such as processors and memory, are vertically stacked. This reduces the distance data travels, improving performance and compactness but complicating fabrication and heat dissipation. Challenges include thermal management, mechanical stress, reliability, manufacturing complexity, interconnect issues, and design difficulties.

Photonic Links and Components Photonic links use light to transmit data on and between chips, offering higher bandwidth and lower energy use than electrical interconnects. Silicon photonics—an emerging technology—enables chip-to-chip communication by integrating optical components on silicon and uses multi-wavelength data transmission with reduced power consumption. This technology is essential for high-performance computing and data centers but faces integration challenges due to material incompatibilities that must be overcome for broad adoption.

Application-Specific Optimization As Moore’s law reaches its limits, future improvements in computing will rely more on optimizing algorithms, hardware, and other technologies for specific applications rather than on general technology scaling. Such optimization will require cheaper and easier ways to explore possible changes to system designs—in particular, by finding ways to ensure that specific changes do not require a redesign of the entire chip. Major technology firms will need to participate in an app store–like model for hardware customization that balances open innovation with their profit motives.

POLICY ISSUES

Talent

The US semiconductor industry faces a significant talent shortage, particularly in hardware design and manufacturing. The recent voiding of up to $7.4 billion in funding from the Creating Helpful Incentives for Producing Semiconductors (CHIPS) and Science Act of 2022 and reductions in government funding for research in general will inevitably shrink the number of new domestic graduates just as the industry will be needing many more new hires. Addressing talent issues requires more and closer collaboration among educational institutions, industry, and government to develop programs that attract and train the next generation of semiconductor engineers and researchers.

Strategic Technology Containment

The United States has intensified export controls and revocation of export authorizations targeting Chinese semiconductor firms and key software and equipment for design and fabrication. This has had a disruptive impact on China’s semiconductor ecosystem, at least in the short term, and its broader ambitions in AI and advanced computing have been impacted. However, these actions may have the unintended impact of decreasing Chinese dependence on Western technology.

Geopolitical Risks and Supply Chain Resilience

Diversifying supply chains and investing in domestic chip-manufacturing capacity is critical for mitigating geopolitical risks linked to the concentration of chip-manufacturing capacity in Taiwan. The United States has taken initial steps to address this with the CHIPS and Science Act, which earmarked $52.7 billion for semiconductor manufacturing, research, and workforce development, as well as tax credits to encourage private investment. Full implementation has not yet occurred, partly because not enough time has elapsed and partly because the appropriations the act called for have not been fully funded.

REPORT PREVIEW: Semiconductors

Faculty Council Advisor

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Mark A. Horowitz
Author
Mark A. Horowitz

Mark A. Horowitz is the Yahoo! Founders Professor in the School of Engineering and professor of electrical engineering and computer science at Stanford University. His research has contributed to early RISC (reduced instruction set computer) microprocessors, multiprocessor designs, and high-speed interfaces, and he currently works to create new agile design methodologies for analog and digital VLSI (very-large-scale integration) circuits. He received his PhD in electrical engineering from Stanford University.

View Bio
mark-horowitz_profilephoto.jpg
Mark A. Horowitz

Mark A. Horowitz is the Yahoo! Founders Professor in the School of Engineering and professor of electrical engineering and computer science at Stanford University. His research has contributed to early RISC (reduced instruction set computer) microprocessors, multiprocessor designs, and high-speed interfaces, and he currently works to create new agile design methodologies for analog and digital VLSI (very-large-scale integration) circuits. He received his PhD in electrical engineering from Stanford University.

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